Interactive labs

Shell & filesystem

• Virtual filesystem terminal
  pwd, ls, mkdir, cp/mv/rm · 22 challenges
• Permissions, umask, PATH & ownership
  rwx · umask · PATH · 22 challenges
• Shell history & reverse-search
  history · Ctrl+R · !! / !n / !$ · 22 challenges
• Absolute vs relative paths
  / · ~ · . / .. · resolve vs cwd · 22 challenges
• Glob / wildcard lab
  * · ? · […] · expand before command · 22 challenges
• man / --help discoverability
  man · --help · whatis · apropos · 22 challenges
• File types & links
  ls -l types · soft vs hard · broken links · 22 challenges
• realpath / readlink
  readlink vs realpath · chains · broken links · 22 challenges
• Dotfiles & config homes
  ls -a · ~/.bashrc · .gitignore · 22 challenges

Processes & text

• Pipes, redirection, xargs & jobs
  | · tee · xargs · 22 challenges
• Process list & signals
  ps · kill · SIGINT / SIGTERM / SIGKILL · 22 challenges
• Job control deep-dive
  Ctrl+Z · jobs · fg / bg · & · 22 challenges
• sort / uniq / cut
  sort · uniq -c · cut -d/-f · log pipelines · 22 challenges
• Here-doc / here-string
  <<EOF · <<'EOF' · <<< · 22 challenges

Scripting

• Script exit codes & control flow
  args · set -e · 23 challenges
• Exit status & && / ||
  $? · && / || · set -e · 22 challenges
• Alias & function lab
  alias vs function · session vs .bashrc · 22 challenges
• Safe scripting checklist
  set -euo pipefail · quoting · --dry-run · 22 challenges

Projects & archives

• Project layout, archives, sed & diff
  tree · find/grep · tar · sed · diff/patch · 22 challenges
• tar vs zip
  tar.gz vs zip · exclude build/ · 22 challenges
• Backup & clean-build
  backup first · dry-run · safe deletes · 22 challenges
• Relative symlink pitfalls
  rel vs abs · tree moves · 22 challenges

Version control

Ordered to match learn_git modules 01–18 (all shipped). Template / submission labs live under Workflow.

• Git mental model
  working tree ↔ index ↔ HEAD · 22 challenges · learn_git 01
• Git graph, staging, stash & rebase
  add/commit · merge/rebase · stash · tags · 22 challenges · learn_git 02
• .gitignore pattern lab
  build/ · *.log · *.vcd · negation · 22 challenges · learn_git 03
• Commit message lab
  subject/body · why over what · 22 challenges · learn_git 04
• git log options
  --oneline · --graph · decorate · path · 22 challenges · learn_git 05
• Safe Git undo
  unstage · restore · soft/mixed/hard · 22 challenges · learn_git 06
• Stash scenarios
  push · pop · apply · drop · -u · 22 challenges · learn_git 07
• Tags (light vs annotated)
  lightweight · annotated · push --tags · 22 challenges · learn_git 08
• Branch naming strategy
  feature/ · fix/ · hotfix/ · base from main · 22 challenges · learn_git 09
• Merge conflict resolver
  markers · ours/theirs · 22 scenarios · learn_git 10
• Rebase vs merge chooser
  8 scenarios · linear vs shared · 22 challenges · learn_git 11
• Cherry-pick lab
  clean pick · conflict · continue/abort · 22 challenges · learn_git 12
• Reflog recovery
  HEAD@{n} · reset recover · branch recover · 22 challenges · learn_git 13
• Blame & bisect
  line attribution · bisect · 22 challenges · learn_git 14
• Remotes, PRs & submodules
  22-question quiz · live GitHub checklist · learn_git 15
• Remote-tracking branches
  origin/main · fetch vs pull · ahead/behind · 22 challenges · learn_git 16
• PR review checklist
  size · tests · hygiene · 8 PRs · 22 challenges · learn_git 17
• Submodule pitfalls
  init · detached HEAD · pin bump · 22 challenges · learn_git 18

Workflow & submission

• Pre-push checklist, Make & env
  check_ready · make · .env · 22 challenges
• Log / failure triage
  fail · env · flake · 12 cases · 22 challenges
• Makefile basics
  targets · deps · .PHONY · vars · 22 challenges
• .env file literacy
  load order · secrets vs commit · 22 challenges
• Template-repo bootstrap
  clone · layout · first status · 22 challenges · learn_git 19
• Dry-run mindset
  --dry-run · echo-first · 22 challenges
• Submission reproducibility
  clean tree · root scripts · logs · 22 challenges · learn_git 20

Number systems & representation

Core path ordered to match learn_digital modules 01–10 (all shipped). verilog-literals is primarily learn_verilog.

• Radix / bit-width converter
  HDL Value · parseLiteral · overflow · 22 challenges · learn_digital 01
• Two’s complement lab
  signed range · negate · wrap · 22 challenges · learn_digital 02
• Overflow / wrap-around
  mod 2^w · signed ov · 22 challenges · learn_digital 03
• ASCII / hex dump literacy
  hex · ASCII gutter · 22 challenges · learn_digital 04
• Gray code converter
  binary ↔ Gray · FIFO · 22 challenges · learn_digital 05
• BCD encode / decode
  packed nibbles · invalid A–F · 22 challenges · learn_digital 06
• Parity / XOR checksum
  even/odd · reduce XOR · 22 challenges · learn_digital 07
• Fixed-point Qm.n
  int vs frac · scale 2^-n · 22 challenges · learn_digital 08
• Bit-field extract / insert
  slice · mask · pack · 22 challenges · learn_digital 09
• Endian packing
  big vs little · pack/unpack · 22 challenges · learn_digital 10
• Verilog literal decoder
  HDL parseLiteral · 28 challenges · b/o/d/h · 's · X/Z · learn_verilog

Boolean algebra & minimization

• Truth-table builder
  2–10 vars · SOP/POS · 22 challenges
• K-map minimizer (2–6 vars)
  Gray code · planes for 5–6 · 0/1/X · 26 challenges
• Boolean law playground
  De Morgan · absorption · step rewrites · 22 challenges
• SOP ↔ POS converter
  minterms · maxterms · 22 challenges
• Don’t-care minimization
  ON · DC · OFF · 22 challenges
• Static / dynamic hazards
  static-1 · static-0 · dynamic · 22 challenges

Gates & combinational blocks

• Gate composer
  HDL gate-net · AND/OR/XOR/NOT · 29 challenges
• Mux / decoder / encoder explorer
  mux 2:1–16:1 · decode →16 · encode 8→3 · 28 challenges
• Priority encoder & comparator
  high/low priority · EI/EO · signed vs unsigned · 22 challenges
• Half / full adder builder
  HA · FA · 2×HA compose · ripple · 22 challenges
• XOR parity tree
  balanced reduce · log₂N vs N−1 · 22 challenges
• Tri-state / bus contention
  high-Z · OE · contention X · 22 challenges
• Barrel shifter
  SLL/SRL/SRA · rotate · mux stages · 22 challenges
• Seven-segment decoder
  hex nibble · a–g · CC/CA · 22 challenges

HDL structure & operators

learn_verilog path ordered first (modules 01–13). Remaining rows are primarily learn_systemverilog.

• Module / port diagram
  HDL parse · ports · instances · 22 challenges · learn_verilog 01
• Verilog literal decoder
  HDL parseLiteral · 28 challenges · b/o/d/h · X/Z · learn_verilog 02
• Classic wire vs reg
  IEEE 1364 · assign vs always · 22 challenges · learn_verilog 03
• ANSI vs non-ANSI ports
  1995 vs 2001 · side-by-side · 22 challenges · learn_verilog 04
• Operator playground
  bitwise vs logical · concat · reduce · shifts · 22 challenges · learn_verilog 05
• Parameter / width explorer
  #(.WIDTH) · $clog2 · derived buses · 22 challenges · learn_verilog 09
• Named vs positional connections
  .port(sig) · order hazards · 22 challenges · learn_verilog 10
• localparam vs parameter
  #() override · localparam · defparam · 22 challenges · learn_verilog 11
• Generate / replication explorer
  for / if generate · genvar · 22 challenges · learn_verilog 12
• One-driver / multi-driver
  contested nets · single-driver RTL · 22 challenges · learn_verilog 13
• Typedef / enum / packed struct
  typedef · enum · packed vs unpacked · 22 challenges · learn_systemverilog 03
• Multi-dimensional arrays
  packed · unpacked · mixed mem · 22 challenges · learn_systemverilog 04
• bit vs logic (2-state / 4-state)
  X/Z · collapse · &/| prop · 22 challenges · learn_systemverilog 01
• Signed / unsigned width
  $signed · extend · compare · 22 challenges · learn_systemverilog 05

SystemVerilog design constructs

Ordered to match learn_systemverilog modules 02, 06–12 (all shipped). Types / arrays live under HDL structure (modules 01, 03–05).

• always_comb / always_ff / always_latch
  intent · latch cues · legacy @(*) · 22 challenges · learn_systemverilog 02
• Interface + modport sketch
  bundle · src/dst · connect · 22 challenges · learn_systemverilog 06
• Package / import explorer
  import * · :: · package vs module · 22 challenges · learn_systemverilog 07
• unique / priority case
  overlap · incomplete · unique0 · 22 challenges · learn_systemverilog 08
• inside / wildcard equality
  inside · ==? · !=? · 22 challenges · learn_systemverilog 09
• Checker / bind sketch
  checker · bind · vs module · 22 challenges · learn_systemverilog 10
• IEEE construct → version map
  1364 · 1800 · logic / always_ff · 22 challenges · learn_systemverilog 11
• 1364 → 1800 migration quiz
  wire/reg→logic · always_* · ANSI · 22 challenges · learn_systemverilog 12

Combinational design hygiene

• Combo style / latch-risk checker
  assign vs always/case · inferred latch · 22 challenges · learn_verilog 07
• Sensitivity-list explorer
  @(*) · incomplete · posedge/async · 22 challenges · learn_verilog 06

Clocks, registers & timing

• Clock-edge stepper
  HDL session · ↗posedge · signal trace · 22 challenges
• Blocking vs non-blocking
  side-by-side = vs <= · 20 challenges · learn_verilog 08
• Reset strategy timelines
  sync vs async · mid-cycle · 22 challenges
• Setup / hold explainer
  tsu / th windows · drag DΔ · 22 challenges
• CDC / 2-FF synchronizer
  metastability · two-flop · 22 challenges
• Clock enable vs gated clock
  CE · AND-gate risk · ICG · 22 challenges
• Shift-register lab
  SISO · SIPO · PISO · PIPO · 22 challenges · learn_verilog 15 · learn_spi 05
• Counter lab
  up · down · modulo · enable · Gray · 22 challenges · learn_verilog 14

Waveforms & debug literacy

learn_iverilog modules 04–06, 09–10 (shipped). Shared waves also used by protocol courses.

• Waveform lab
  HDL session waves · cursor · watch list · 22 challenges · learn_uart 10 · learn_spi 08 · learn_i2c 08 · learn_iverilog 09
• Testbench anatomy explorer
  DUT vs tb · reg/wire · $display / $finish · 22 challenges · learn_uvm2017 03
• Delay / event / wait
  #delay · @event · wait · 22 challenges · learn_iverilog 04
• Task vs function vs always
  task · function · always_ff/comb · 22 challenges · learn_iverilog 05
• Fork / join sketch
  join · join_any · join_none · 22 challenges · learn_iverilog 06
• GTKWave cursor literacy
  markers · zoom · SST add · 22 challenges · learn_iverilog 10

FSM & control

• FSM designer + stepper
  Moore/Mealy · editable table · step stream · 22 challenges · learn_spi 06 · learn_i2c 06
• State encoding lab
  binary · one-hot · Gray · Hamming · 22 challenges
• Sequence detector playground
  Mealy/Moore · overlap · step stream · 22 challenges
• Ring / Johnson counter
  one-hot ring · twisted-ring · 22 challenges · learn_digital 33
• LFSR / PRBS stepper
  taps · PRBS · period 2ⁿ−1 · 22 challenges · learn_digital 34

Arithmetic & datapath

• Ripple-carry adder animator
  FA chain · step carry · 4/8-bit · 22 challenges
• Carry-lookahead generate & propagate
  G/P · expanded carries · 4/8-bit · 22 challenges
• Array multiplier grid
  partial products · 3×3/4×4 · 22 challenges
• ALU operation explorer
  opcode · Y · Z/N/C/V · 4/8-bit · 22 challenges
• Carry-select adder sketch
  dual path · mux on C4 · 22 challenges · learn_digital 39
• Booth encode grid
  radix-4 · digits 0,±1,±2 · 22 challenges · learn_digital 40
• Signed arithmetic / overflow
  two’s complement · NZCV · 22 challenges · learn_digital 41

Memory, FIFO & cache

• RAM / ROM address map
  16×8 · R/W flash · $readmemh · 22 challenges
• FIFO pointer & flags
  sync FIFO · wr/rd · empty/full · 22 challenges · learn_uart 06
• Cache hit/miss walkthrough
  direct-mapped · tag/index/offset · 22 challenges
• Dual-port RAM
  independent ports · collisions · 22 challenges
• Byte-enable memory
  be[3:0] · partial store · 22 challenges
• Async FIFO (Gray pointers)
  cross-clock · Gray sync · empty/full · 22 challenges

Hierarchy, buses & integration

• Block-diagram integrator
  typed ports · click-to-wire · 22 challenges
• Bus handshake animator
  valid/ready · stalls · 22 challenges · learn_uart 07
• Pipeline stall / forward
  RAW hazard · stall or forward · 22 challenges

Coding standards & synthesizability

• Synthesizability linter
  HDL engine lint · #delay · latch · 22 challenges · learn_verilog 16
• Naming / style checker
  lintStyle · clk / rst_n · always_ff · 22 challenges · learn_verilog 17

Protocols (conceptual)

learn_uart / learn_spi / learn_i2c protocol labs shipped (see module tags). Shared datapath labs: FIFO · handshake · shift-reg · FSM · waves.

• UART frame animator
  start/data/parity/stop · 22 challenges · learn_uart 01
• Spec → RTL checklist
  ports/blocks → RTL skeleton · UART/SPI/I²C · 22 challenges · learn_uart/spi/i2c 02
• Baud / clock divider
  sysclk → baud_tick / clk_div · 22 challenges · learn_uart 03
• UART oversampling
  16× mid-bit · majority · start center · 22 challenges · learn_uart 04
• UART error cases
  framing · parity · overrun · 22 challenges · learn_uart 05
• SPI transaction stepper
  Mode 0 · CS/SCLK/MOSI/MISO · 22 challenges · learn_spi 01
• SPI CPOL/CPHA modes
  mode 0–3 edge matrix · 22 challenges · learn_spi 03
• SPI multi-CS / daisy
  independent CS vs daisy-chain · 22 challenges · learn_spi 04
• I²C start/addr/ack explorer
  START · addr+R/W · ACK/NACK · 22 challenges · learn_i2c 01
• I²C open-drain model
  open-drain vs push-pull · wired-AND · 22 challenges · learn_i2c 03
• I²C clock stretch
  slave holds SCL · master waits · 22 challenges · learn_i2c 04
• I²C repeated start
  Sr vs Stop+Start · read-after-write · 22 challenges · learn_i2c 05
• Basic TB vs UVM map
  wiggle-pins vs transaction/agent · 22 challenges · learn_uvm2017 02 · learn_uart 11 · learn_spi 09 · learn_i2c 09

SV testbench & assertions (conceptual)

• Class / inheritance sketch
  object vs component · extends · 22 challenges · SV TB literacy
• Constraint / random lite
  dice + constraint · randomize() · 22 challenges · learn_uvm2017 12
• Coverpoint / bins sketch
  coverpoint → bins → holes · 22 challenges · learn_verification_planning_management 04
• SVA implication timeline
  a |-> b / |=> · pass/fail/vacuous · 22 challenges · learn_uvm2017 15
• Virtual interface wiring
  interface → DUT → virtual handle · 22 challenges · SV TB literacy
• Self-checking TB pattern
  stimulus → expect → pass/fail · 22 challenges · learn_uart 08 · learn_spi 07 · learn_i2c 07 · learn_iverilog 08
• TB clock + reset patterns
  clock gen · reset assert/deassert · 22 challenges · learn_uart 09 · learn_verilator 05
• File / vector I/O
  $readmemh stim/exp · apply loop · 22 challenges · SV TB literacy

UVM 2017 methodology (sketches)

learn_uvm2017 browser sketches for IEEE 1800.2-2017 UVM literacy (module tags). Fidelity remains offline UVM (module 22). TB anatomy / waves also under Waveforms.

• Testbench layer diagram
  test → env → agent + scoreboard → vif → DUT · 22 challenges · learn_uvm2017 01
• UVM phase timeline
  build → connect → run → check → report · 22 challenges · learn_uvm2017 04 · learn_pyuvm 05
• Factory override sketch
  type/inst override · who gets constructed · 22 challenges · learn_uvm2017 05 · learn_pyuvm 06
• ConfigDB key path
  set/get by path + field · 22 challenges · learn_uvm2017 06 · learn_pyuvm 08
• Agent anatomy
  sequencer / driver / monitor · active vs passive · 22 challenges · learn_uvm2017 07 · learn_pyuvm 07
• TLM port wiring
  seq_item / put / get / analysis · 22 challenges · learn_uvm2017 08
• Sequence → driver flow
  item → sequencer → driver → DUT · 22 challenges · learn_uvm2017 09 · learn_pyuvm 07
• Objection raise/drop
  who holds run open · raise/drop · 22 challenges · learn_uvm2017 10 · learn_pyuvm 08
• Plusargs / CLP
  +UVM_TESTNAME · seed/verbosity knobs · 22 challenges · learn_uvm2017 11
• Scoreboard expect/actual
  predict vs observe · orphans · 22 challenges · learn_uvm2017 13 · learn_pyuvm 09
• Register model map
  block→reg→field · front-door vs back-door · 22 challenges · learn_uvm2017 14
• Multi-agent env
  two+ agents · shared scoreboard · 22 challenges · learn_uvm2017 16 · learn_pyuvm 09
• Virtual sequence
  vsequencer refs · seq vs parallel · 22 challenges · learn_uvm2017 17
• Callbacks sketch
  pre/post hooks without subclassing · 22 challenges · learn_uvm2017 18
• UVM reporting ladder
  severity · verbosity · ID filter · 22 challenges · learn_uvm2017 19
• Protocol checker sketch
  bus rules vs scoreboard roles · 22 challenges · learn_uvm2017 20 · learn_spi 09
• VIP anatomy
  agent + checker + coverage + docs · 22 challenges · learn_uvm2017 21 · learn_uart 12 · learn_i2c 09

Python / cocotb / pyuvm (sketches)

learn_pyuvm modules 01–04 pyuvm/cocotb labs shipped. Shared UVM 2017 sketches 05–09 live under UVM 2017 methodology. Fidelity is offline (module 10). Optional literacy: tb-anatomy / tb-vs-uvm-map.

• Python async TB sketch
  async def test · await timeline · 22 challenges · learn_pyuvm 01
• cocotb triggers
  RisingEdge · Timer · First / Combine · 22 challenges · learn_pyuvm 02
• cocotb DUT handle
  dut.path hierarchy · .value peek/poke · 22 challenges · learn_pyuvm 03
• cocotb vs UVM map
  pyuvm / cocotb ↔ SV UVM roles · 22 challenges · learn_pyuvm 04
• pytest assert / golden
  expect vs actual · 22 challenges
• Stimulus as data
  Python vector lists · 22 challenges
• cocotb Clock helper
  Clock.start · edge timeline · 22 challenges
• cocotb BinaryValue
  width + value → bits · 22 challenges
• cocotb scoreboard sketch
  expect queue vs observe · 22 challenges

Formal verification (conceptual)

learn_formal — assert/assume/cover, BMC, CEX, induction, vacuity sketches. Engines stay offline.

• Assert / assume / cover
  property roles · 22 challenges
• Formal BMC bound
  bound k vs bugAt · 22 challenges
• Formal counterexample
  step CEX wave · 22 challenges
• Formal induction sketch
  base + step · 22 challenges
• Formal vacuity
  vacuous pass · 22 challenges

Verification planning (lightweight)

• Coverage / plan checklist
  feature → scenario → coverage · 22 challenges · learn_verification_planning_management 01
• Feature × scenario matrix
  traceability grid P/C/gap · 22 challenges · learn_verification_planning_management 03
• Coverage closure planner
  hole → next test idea · 22 challenges · learn_verification_planning_management 05
• Regression triage board
  fail / flake / new / env · 22 challenges · learn_verification_planning_management 08
• Test taxonomy planner
  directed / random / stress / corner · 22 challenges · learn_verification_planning_management 02
• Risk-based plan matrix
  risk × impact → P0/P1/P2/defer · 22 challenges · learn_verification_planning_management 06
• Sign-off criteria
  coverage · bug bar · stability · 22 challenges · learn_verification_planning_management 11
• Seed / config / tags
  replay metadata · 22 challenges · learn_verification_planning_management 07
• CI / farm regression flow
  local → CI → farm · 22 challenges · learn_verification_planning_management 10
• VIP handoff checklist
  docs + API + self-test · 22 challenges · learn_verification_planning_management 12

Simulation literacy (conceptual)

learn_verilator 01–09 and learn_iverilog toolchain labs shipped. TB/wave literacy also under Waveforms. Offline: Verilator m10 · iverilog m11.

• iverilog vs Verilator chooser
  when to pick each tool · 22 challenges · learn_verilator 01
• Compile → elaborate → run
  iverilog / Verilator stage diagram · 22 challenges · learn_verilator 02 · learn_iverilog 01
• Verilator lint lab
  -Wall · UNUSED/WIDTH/LATCH · 22 challenges · learn_verilator 03
• C++ TB / DPI sketch
  Verilator C++ TB vs SV TB · 22 challenges · learn_verilator 04
• Verilator trace
  --trace / --trace-fst · dump · 22 challenges · learn_verilator 06
• Wave dump literacy
  VCD vs FST roles · 22 challenges · learn_verilator 07 · learn_iverilog 09
• Verilator public
  /*verilator public*/ · hierarchy · 22 challenges · learn_verilator 08
• Verification metrics board
  pass rate · coverage % · bug escape · 22 challenges · learn_verilator 09 · learn_verification_planning_management 09
• iverilog flags lab
  -g2005/-g2012 · -Wall · -o · +incdir · 22 challenges · learn_iverilog 02
• iverilog timescale
  `timescale vs timeunit · 22 challenges · learn_iverilog 03
• vvp plusargs
  $test$plusargs · $value$plusargs · 22 challenges · learn_iverilog 07

Browser HDL simulator (guided)

Practice surface: HDL Simulator · syllabus: learn_hdl_simulator

• Simulator UI tour
  Files · Hierarchy · Signals · Wave · Console · 22 challenges · learn_hdl_simulator 01
• Hello DUT in browser
  tiny module · Run / Stop / Reset · 22 challenges · learn_hdl_simulator 02
• Step & continue
  Step · Continue · $stop / breakpoints · 22 challenges · learn_hdl_simulator 03
• Poke / force / release
  live drive vs force hazards · 22 challenges · learn_hdl_simulator 04
• Full-sim waves
  add signals · C1/C2 · radix · 22 challenges · learn_hdl_simulator 05
• Multi-file project
  top · defines · +incdir · profiles · 22 challenges · learn_hdl_simulator 06
• Golden compare
  diff @ C1 · JSON/VCD export · 22 challenges · learn_hdl_simulator 07